1. Field of the Invention
The present invention relates to an input/output buffer, and more particularly, to an input/output buffer capable of occupying reduced wafer area.
2. Description of the Related Art
Conventionally, most IC devices are driven by a system voltage in the range of 0-5V. In these IC devices, the high-voltage logic signals are therefore set at the system voltage and the low-voltage logic signals are set at the ground voltage. With advances in semiconductor technology, however, the system voltage can be now reduced to 3.3V because the gate oxide layers in the IC device are thinner. Still lower system voltage may be possible in the future. In practice, however, an New 3.3V IC device is usually used in conjunction with some older 5V peripheral devices. For instance, an New 3.3V VGA (video graphic adapter) IC may be used in conjunction with other older 5V peripheral devices in a personal computer. Compatibility between the new 3.3V devices and the older 5V devices can thus be a problem.
FIG. 1 is a schematic circuit diagram showing the circuit structure of a conventional I/O buffer 14 used in a 3.3V IC device. As shown, the I/O buffer 14 is coupled to an input buffer 16 and an I/O pad 20 of an IC device. The I/O buffer 14 is composed of a first circuit 10, a second circuit 12, a PMOS transistor P1, and an NMOS transistor N1. When the I/O buffer operates in input mode, both the PMOS transistor P1 and the NMOS transistor N1 must be switched to a non-conducting state. To do this, the first circuit 10 outputs a high-voltage signal, for example 3.3V, to the gate of the PMOS transistor P1, thereby switching the PMOS transistor P1 to a non-conducting state. Meanwhile, the second circuit 12 outputs a low-voltage signal, for example 0V, to the gate of the NMOS transistor N1, thereby switching the NMOS transistor N1 to a non-conducting state.
However, if the I/O pad 20 receives a 5V input logic signal, it subjects the PMOS transistor P1 to a gate voltage of 3.3V, a drain voltage of 5V, and a source voltage of 3.3V. Since the gate voltage (3.3 V) is lower than the drain voltage (5 V) at the PMOS transistor P1, the gate voltage switches the PMOS transistor P1 to a reverse conducting state. Moreover, since the PMOS transistor P1 is formed on an N-type substrate and its source and drain are both P-type, a PN junction diode is formed between its drain and the N-well. Furthermore, since the drain of the PMOS transistor P1 is connected to the I/O pad 20, now receiving the 5 V input logic signal, higher than the 3.3V system voltage, and the substrate thereof is connected to the 3.3V system voltage, the PN junction diode is subjected to a forward bias, causing an undesired large current to flow between the external 5V source and the internal 3.3V source.
As a solution, an improved I/O buffer for the 3.3V IC is disclosed. FIG. 2 is a schematic diagram showing an I/O buffer capable of accepting an input logic signal voltage higher than the system voltage. The P-gate control circuit 32 conveys the first gate control signal Vp to the PMOS transistor Q3 of the I/O circuit. The N-well control circuit 34 adjusts the voltage at the floating N-well of the PMOS transistor Q3 according to the input voltage at the I/O pad 36. Undesired current leakage is thus prevented. In this I/O buffer, however, transistors Q5 and Q6 are required to follow design rules for electrostatic discharge (ESD) protection because the transistors Q5 and Q6 of the P-gate control circuit 32 are connected to the I/O pad 36 directly. Thus, it occupies a larger wafer area.